Part Select or Slice implementation in SV

To optimize the following system verilog code:

sample[0] = &dq[7:0];

sample[1] = &dq[15:8];

sample[2] = &dq[23:16];

sample[3] = &dq[31:24];

...

so on for 64-bit packed array dq. This was simplified by using for loop with system verilog slice or part select of packed arrays as:

for (int i=0,j=0; i<ST_W; i+=8, j++) begin //ST_W=DATA_WIDTH/16

sample[j] = &dq[i+:8];

end

The index i represents position of the slicing which is added to a constant 8 to determine the size of part select or slice. Thus, the code can be reused for any data width with reduced code density and easy readability.