Default seed of VCS can

In system verilog,if a packet class is created with rand items and every independent run with vcs generates the same values for rand items.

 

The above code having three 2-bit rand variables, when run with vcs command:

> vcs –sverilog –R test.sv

will output same value a=2, b=2, c=1 for all 10 iterations even when run again with the same above command. This is because, every vcs executes the test always with the default seed, which is equal to 1. And hence, randomize() function will always execute for constant seed (=1) in this process.

Utilizing the characteristics of rand type, the above code can be modified to dump different values of a, b, c in each iteration when run with the vcs command.

This will dump out unique values of a, b and c in each iteration.

The same can be run by changing RNG value for seeding from the command line using +ntb_random_seed. For running regression this is the best solution.

fork…join_none and for loop

An interesting case with fork…join_none block defined inside a for loop in system verilog is shown here as an example:

 

The intended result of this code is to display the iteration count value, i, from 0 to 3. That is, each call to system task, $display, will hold a unique value of i.

But the output of the above example is:

This can be explained as: Each iteration in the for loop initiates a parallel thread to display the value of variable i (iteration count). Because of join_none keyword, none of the threads (blocks) are waited for completion of their execution. So the immediately next statement after the for loop (zero time delay) is executed, which in this case is $display (“THE END”) system task and hence is the first line of output observed.

By the end of execution of for loop (zero time), the value of i is 4. This is the value that gets updated across all the threads (blocks) that has been initiated to display the value of i. Even before the threads begin to start executing the value of i has been changed to 4, which is what is observed in the output. This result implies that variable i is a static variable.

For this particular example replacing join_none by join statement will result into the expected output. That is, each parallel thread will display unique value of i and the output seen is i changing in consecutive order from 0 to 3.

In case join_none statement cannot be replaced because, say for example, of time consuming user defined task being called and the logic requires that no time is to be spent before executing the next statement following the for loop, then create an automatic variable inside a for loop and assign i to it before starting the fork…join_none block.

Here, keyword automatic can be ignored as well. Variable k is roughly similar to C automatic variable. Now, the lifetime of automatic variable k is the lifetime of each fork...join_none block. So each block will have a unique value of k, which doesn’t get changed even after completion of for loop. 

Part Select or Slice implementation in SV

To optimize the following system verilog code:

sample[0] = &dq[7:0];

sample[1] = &dq[15:8];

sample[2] = &dq[23:16];

sample[3] = &dq[31:24];

...

so on for 64-bit packed array dq. This was simplified by using for loop with system verilog slice or part select of packed arrays as:

for (int i=0,j=0; i<ST_W; i+=8, j++) begin //ST_W=DATA_WIDTH/16

sample[j] = &dq[i+:8];

end

The index i represents position of the slicing which is added to a constant 8 to determine the size of part select or slice. Thus, the code can be reused for any data width with reduced code density and easy readability.

GVIM syntax highlight for systemverilog

Gvim syntax file for SystemVerilog & AVM can be downloaded from the following link: http://www.sibridgetech.com/download/systemverilog_avm.zip  

For gvim (portable) installed on windows, the following steps need to be followed:

1. The unzipped file needs to saved in ...\GVimPortable\App\vim\vim71\syntax directory.
2. Then, edit the file ..\GVimPortable\App\vim\vim71\filetype.vim to add the following lines (search line containing "verilog" in the file and insert the below lines beneath it):

" System Verilog
au BufNewFile,BufRead *.sv,*.svh setf systemverilog_avm

3. Close and open any systemverilog file having .sv and/or .svh extension.

TLM in OVM

Here's a very good demonstration of the need and importance of TLM in OVM.

ಅತ್ತು ಅತ್ತು ಮತ್ತತ್ತು

ಯಕ್ಷನ ವಿರಹದಿ೦ದ ಬೆ೦ದ ಯಕ್ಷಿಯ ಚಿತ್ರ - ಬೇ೦ದ್ರೆಯವರ ದೃಷ್ಟಿಯಲಿ  :

ಅತ್ತು ಅತ್ತು ಮತ್ತತ್ತು ಕೆದರಿಕೊ೦ಡಿಹುದು ಕಣ್ಣ ಪೊಗರು
ಬೆಚ್ಚನುಸಿರನು೦ಡು೦ಡು ಸೊಪ್ಪೆಯಾಗಿಹುದು ತುಟಿಯ ಚಿಗುರು
ಗಲ್ಲದಲ್ಲಿ ಕೈ, ಓರೆ ಮೋರೆ, ನಿಡಿಗೂದಳುದ್ದ  ಚಿ೦ತೆ
ಮೋಡ ಮುಸಕಲಿರೆ ಮ೦ಕುಕವಿದ ಆ ದೀನ ಚ೦ದ್ರನ೦ತೆ II

Best poll question ever

Best poll question I've come across (Adult Discretion Advised), which beats even the daily polls by Sagarika "faze the nation" Ghose on CNN-IBN.

Note (DON'T SAY I DIDN'T WARN):

The first link leads to "Adult Discretion Advised" kind of site, so please follow the advise, especially when you are in office. 

Life is Just is

Like a small stone wading thru the water to the depth -- half resisting but willing, half willing but resisting -- all the while following the natural laws, I've let myself go thru new phase of life. I only fulfill the natural laws of life without questioning and without seeking for answers.

Life is neither a question nor an answer to an unknown question. It is just is.

Terrorism LeT loose

Few good articles analysing today's heinous act by Pakistan terrorists:

1. Prem Panicker's take on today's terrorist attack on SL cricketers:
http://www.rediff.com/cricket/2009/mar//03prem-panicker-sri-lanka-team-attacked-in-pakistan.htm

2. B.Raman, India's best defence analyst, hints that this attack might be ordered by LTTE and executed by fringe terrorist-group in Pakistan.
http://ramansterrorismanalysis.blogspot.com/2009/03/hum-repays-old-debt-to-ltte-in-lahore.html

All this after Imran Khan had given strong/personal assurance to India about terrorists not attacking any cricketers if they tour Pakistan.