In system verilog,if a packet class is created with rand items and every independent run with vcs generates the same values for rand items.
The above code having three 2-bit rand variables, when run with vcs command:
> vcs –sverilog –R test.sv
will output same value a=2, b=2, c=1 for all 10 iterations even when run again with the same above command. This is because, every vcs executes the test always with the default seed, which is equal to 1. And hence, randomize() function will always execute for constant seed (=1) in this process.
Utilizing the characteristics of rand type, the above code can be modified to dump different values of a, b, c in each iteration when run with the vcs command.
This will dump out unique values of a, b and c in each iteration.
The same can be run by changing RNG value for seeding from the command line using +ntb_random_seed. For running regression this is the best solution.
